Comparison of Biphase Spreading to Quadriphase Spreading in DS CDMA Systems

EEcient series that are used to calculate the bit error probabilities for biphase spread and quadriphase spread, BPSK modulated, asynchronous DS CDMA systems are derived. These series are then used to investigate the degradation in the performance of both systems due to synchronization errors. The analysis requires the characteristic functions of the multiple access interference and of the self interference and these functions have been expressed in terms of the special functions of mathematical physics. It is found that both systems have comparable performances when synchronization errors are considered. Thus, as far as system capacity is concerned, quadriphase spreading does not ooer any advantage relative to the simpler biphase spread system. In this paper, we present a performance analysis for both biphase and quadriphase spread, BPSK modulated, asyn-chronous direct sequence code division multiple access (DS CDMA) systems in additive white Gaussian noise environments when chip timing and carrier phase errors are present. We use the Fourier series expansion method of 1] to derive innnite series for the probability of symbol error for both systems and nd the system capacities from these expressions for a given signal to noise ratio and maximum allowable bit error rate. There have been a number of papers on the calculation of error probabilities for DS CDMA systems in the literature 2-5]. This paper diiers from the rest in a number of ways. First, the majority of these papers use the Gaussian approximation for the probability of error calculations claiming that the exact calculation is computationally diicult 4]. In this paper, however, we derive an exact expression for the probability of error that is very fast to compute. In fact, a whole bit error rate curve with ten points can be generated in approximately two minutes on a Sun Sparc IPX work station. Furthermore, all of the other papers in the literature assume that perfect synchronization of the chip timing and carrier phase is established in the system of interest. However, here we do not neglect the presence of synchronization errors. In fact, our aim here is to investigate the performance loss in the system due to various levels of synchronization errors. Finally, we show that a static synchronization error, be it a chip timing error, a carrier phase error or both, can be represented as an effective processing gain loss for both biphase spread and quadriphase spread systems. The rest of this paper is organized …